Unit 3: Multiplexers, decoders and sequential circuits

A multiplexer (MUX) is a data selector: it has 2ⁿ data inputs, n select lines and one output. The select lines decide which input reaches the output. A demultiplexer (DEMUX) does the reverse: one input is routed to one of 2ⁿ outputs chosen by the select lines.

• 4:1 MUX output: Y = S₁'S₀'I₀ + S₁'S₀I₁ + S₁S₀'I₂ + S₁S₀I₃
• Implementing a function with a MUX: connect the function's variables to the select lines and tie each data input to 0 or 1 according to the truth table. An n-variable function needs a 2ⁿ:1 MUX (or a 2ⁿ⁻¹:1 MUX with one variable on the data inputs).

• A decoder converts n input lines into up to 2ⁿ output lines, activating exactly one output for each input combination. A 3-to-8 decoder is used for selecting memory chips. Decoders can also implement functions: each output is a minterm.
• An encoder does the opposite: 2ⁿ input lines to n output lines. An 8-to-3 (octal-to-binary) encoder outputs the binary code of the active input.
• A priority encoder gives the code of the highest-priority input when several inputs are active at once.

A latch is a 1-bit memory element that responds to its inputs whenever it is enabled (level-triggered). A flip-flop is a clocked latch that changes state only at the clock edge (edge-triggered), which makes timing predictable.

The S-R (Set-Reset) flip-flop has inputs S and R and outputs Q and Q'.

The S = R = 1 condition is not allowed because both outputs try to become equal, breaking the rule that Q and Q' are complements.

The J-K flip-flop removes the invalid state of S-R: when J = K = 1 the output toggles (Q becomes Q').

Characteristic equation: Q(next) = JQ' + K'Q. Race-around condition: in a level-triggered J-K flip-flop with J = K = 1, if the clock pulse stays high longer than the gate delay, the output keeps toggling many times during one pulse, so the final state is unpredictable. Ways to remove it: keep the clock pulse width shorter than the propagation delay, use edge triggering, or use a Master-Slave J-K flip-flop.

It is two J-K flip-flops in series. The master is enabled when the clock is high; the slave is enabled when the clock is low (through an inverted clock).

Because the output can change only once per clock cycle, the race-around problem disappears.

• D (Data/Delay) flip-flop: one input D; the output takes the value of D at the clock edge: Q(next) = D. It is made from an S-R or J-K flip-flop with S = D and R = D'. It removes the invalid state and is used in registers.
• T (Toggle) flip-flop: one input T; if T = 0 the output stays the same, if T = 1 it toggles: Q(next) = T ⊕ Q. It is made from a J-K flip-flop with J = K = T and is used in counters.

• Registers: a group of flip-flops stores a binary word (an 8-bit register uses 8 flip-flops).
• Shift registers: move data left or right for serial-parallel conversion.
• Counters: count clock pulses (T or J-K flip-flops).
• Frequency division: a T flip-flop divides the clock frequency by 2.
• Memory: static RAM cells are flip-flops.
• Debouncing switches and storing status flags in a CPU.