Unit 2: Combinational logic circuits
Computer Architecture notes · PTU syllabus (UGCC2502)
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Unit summary
Combinational circuits are circuits whose output depends only on the present inputs — they have no memory. Adders inside the processor, data selectors and code converters are all combinational circuits.
This unit covers adders and subtractors, the parallel binary adder, multiplexers, demultiplexers, encoders and decoders, and how to implement Boolean functions using a multiplexer.
After this unit you can
- Design half and full adders and subtractors from their truth tables
- Explain a parallel binary adder and an adder/subtractor
- Describe multiplexers, demultiplexers, encoders and decoders
- Implement a Boolean function using a multiplexer
PTU syllabus topics
- Half adder/subtractor
- full adder/subtractor
- parallel binary adder
- binary adder/subtractor
- multiplexers and demultiplexers
- implementing Boolean equations using MUX/DEMUX
- encoders and decoders
Inputs
2 bits (A, B)
3 bits (A, B, carry-in)
Outputs
Sum, Carry
Sum, Carry-out
Sum expression
A ⊕ B
A ⊕ B ⊕ Cin
Use
Adding the least significant bits
Chaining bits in a parallel adder
Topic 1
Combinational circuits
A combinational circuit is built from logic gates; its outputs at any moment depend only on the inputs at that moment. Design follows a fixed procedure.
- 1State the problem
- 2Decide inputs and outputs
- 3Draw the truth table
- 4Write and simplify expressions
Using K-maps
- 5Draw the logic circuit
Topic 2
Half adder and full adder
A half adder adds two bits A and B and gives a Sum and a Carry.
- Sum = A ⊕ B, Carry = A·B
- It cannot add a carry coming in from a previous stage.
A full adder adds three bits: A, B and the carry-in Cin.
- Sum = A ⊕ B ⊕ Cin
- Cout = AB + Cin(A ⊕ B)
- A full adder can be built from two half adders and an OR gate.
| A | B | Cin | Sum | Cout |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
(Partial table: the full table has 8 rows.)
Topic 3
Half and full subtractors
A half subtractor subtracts B from A: Difference = A ⊕ B, Borrow = A'B. A full subtractor also handles a borrow-in (Bin): Difference = A ⊕ B ⊕ Bin, Borrow = A'B + Bin(A ⊕ B)'.
Exam tip
Notice that Sum and Difference have the same expression; only the carry/borrow expressions differ. Examiners often ask you to compare them.
Topic 4
Parallel binary adder and adder/subtractor
A parallel binary adder adds two n-bit numbers using n full adders connected in a chain: each stage's carry-out feeds the next stage's carry-in (a ripple-carry adder). A 4-bit adder uses four full adders. A binary adder/subtractor uses XOR gates on the B inputs and a control line M:
- M = 0: XOR passes B unchanged and Cin = 0, so the circuit computes A + B.
- M = 1: XOR inverts B (1's complement) and Cin = 1 adds one, giving the 2's complement of B, so the circuit computes A − B.
Example
0101 (5) − 0011 (3): 2's complement of 0011 is 1101. 0101 + 1101 = 1 0010; discard the final carry, result 0010 = 2.
Topic 5
Multiplexers and demultiplexers
A multiplexer (MUX) is a data selector: it has 2ⁿ data inputs, n select lines and one output. The select lines decide which input reaches the output. A demultiplexer (DEMUX) does the reverse: one input is routed to one of 2ⁿ outputs chosen by the select lines.
Inputs
2ⁿ data inputs
1 data input
Outputs
1
2ⁿ
Job
Many-to-one data selector
One-to-many data distributor
Example
4:1 MUX with 2 select lines
1:4 DEMUX with 2 select lines
- 4:1 MUX output: Y = S₁'S₀'I₀ + S₁'S₀I₁ + S₁S₀'I₂ + S₁S₀I₃
- Implementing a function with a MUX: connect the function's variables to the select lines and tie each data input to 0 or 1 according to the truth table. An n-variable function needs a 2ⁿ:1 MUX (or a 2ⁿ⁻¹:1 MUX with one variable on the data inputs).
Topic 6
Encoders and decoders
- A decoder converts n input lines into up to 2ⁿ output lines, activating exactly one output for each input combination. A 3-to-8 decoder is used for selecting memory chips. Decoders can also implement functions: each output is a minterm.
- An encoder does the opposite: 2ⁿ input lines to n output lines. An 8-to-3 (octal-to-binary) encoder outputs the binary code of the active input.
- A priority encoder gives the code of the highest-priority input when several inputs are active at once.
Key terms
- Combinational circuit
- A circuit whose output depends only on present inputs
- Full adder
- Adds three bits (A, B and carry-in)
- Ripple carry
- Carry passing from one adder stage to the next
- Multiplexer
- A data selector with many inputs and one output
- Decoder
- Converts n inputs to one of 2ⁿ outputs
Quick revision
- Half adder: S = A ⊕ B, C = AB. Full adder: S = A ⊕ B ⊕ Cin.
- Full adder = two half adders + OR gate.
- Adder/subtractor uses XOR on B and Cin = M for 2's complement subtraction.
- MUX: many to one; DEMUX: one to many.
- Decoder: n → 2ⁿ; encoder: 2ⁿ → n.
Important exam questions
Practice questions written to the PTU exam pattern for this unit's syllabus: short answers (Section A style) and long answers (Sections B and C style).
Short-answer questions
- Q1.What is a combinational circuit?
- Q2.Write the expressions for the sum and carry of a half adder.
- Q3.Differentiate between a multiplexer and a demultiplexer.
- Q4.What is a priority encoder?
- Q5.How many select lines does a 16:1 multiplexer need?
- Q6.Why is a parallel adder called a ripple-carry adder?
Long-answer questions
- Q1.Design a full adder using its truth table and K-maps, and implement it using two half adders.
- Q2.Explain a 4-bit binary adder/subtractor with a neat diagram.
- Q3.Explain a 4:1 multiplexer and implement F(A, B, C) = Σm(1, 3, 5, 6) using a multiplexer.
- Q4.Explain the working of a 3-to-8 decoder and an 8-to-3 encoder.
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