Unit 3: Sequential logic circuits
Computer Architecture notes · PTU syllabus (UGCC2502)
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Unit summary
Sequential circuits have memory: their output depends on the present inputs and also on what happened before. The basic memory element is the flip-flop, which stores one bit. Registers, counters and computer memory are all built from flip-flops.
This unit covers latches and the R-S, J-K, Master-Slave J-K, D and T flip-flops, the race-around problem and its solution, and the main uses of flip-flops.
After this unit you can
- Distinguish combinational from sequential circuits and latches from flip-flops
- Write the truth table and characteristic equation of each flip-flop
- Explain the race-around condition and how a Master-Slave J-K flip-flop removes it
- List applications of flip-flops
PTU syllabus topics
- Latches
- flip-flops — R-S
- J-K (including race-around condition and its removal)
- Master-Slave J-K
- D flip-flop
- T flip-flop
- applications of flip-flops
- SR flip-flop
- Set/reset; S = R = 1 is not allowed
- JK flip-flop
- Like SR but J = K = 1 toggles the output
- Master-slave JK
- Two stages that remove the race-around problem
- D flip-flop
- Output follows the D input on the clock edge
- T flip-flop
- Toggles when T = 1; used in counters
Topic 1
Sequential circuits, latches and flip-flops
Output depends on
Present inputs only
Present inputs and past state
Memory
None
Yes, flip-flops
Clock
Not needed
Usually needed
Examples
Adder, MUX, decoder
Flip-flop, register, counter
A latch is a 1-bit memory element that responds to its inputs whenever it is enabled (level-triggered). A flip-flop is a clocked latch that changes state only at the clock edge (edge-triggered), which makes timing predictable.
Topic 2
R-S flip-flop
The S-R (Set-Reset) flip-flop has inputs S and R and outputs Q and Q'.
| S | R | Q(next) | Action |
|---|---|---|---|
| 0 | 0 | Q | No change |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | ? | Invalid (forbidden) |
The S = R = 1 condition is not allowed because both outputs try to become equal, breaking the rule that Q and Q' are complements.
Topic 3
J-K flip-flop and the race-around condition
The J-K flip-flop removes the invalid state of S-R: when J = K = 1 the output toggles (Q becomes Q').
| J | K | Q(next) |
|---|---|---|
| 0 | 0 | Q (no change) |
| 0 | 1 | 0 (reset) |
| 1 | 0 | 1 (set) |
| 1 | 1 | Q' (toggle) |
Characteristic equation: Q(next) = JQ' + K'Q. Race-around condition: in a level-triggered J-K flip-flop with J = K = 1, if the clock pulse stays high longer than the gate delay, the output keeps toggling many times during one pulse, so the final state is unpredictable. Ways to remove it: keep the clock pulse width shorter than the propagation delay, use edge triggering, or use a Master-Slave J-K flip-flop.
Topic 4
Master-Slave J-K flip-flop
It is two J-K flip-flops in series. The master is enabled when the clock is high; the slave is enabled when the clock is low (through an inverted clock).
- 1Clock goes high
Master reads J and K; slave is locked
- 2Clock goes low
Master is locked; slave copies the master
- 3Output changes once per clock cycle
Race-around is removed
Because the output can change only once per clock cycle, the race-around problem disappears.
Topic 5
D and T flip-flops
- D (Data/Delay) flip-flop: one input D; the output takes the value of D at the clock edge: Q(next) = D. It is made from an S-R or J-K flip-flop with S = D and R = D'. It removes the invalid state and is used in registers.
- T (Toggle) flip-flop: one input T; if T = 0 the output stays the same, if T = 1 it toggles: Q(next) = T ⊕ Q. It is made from a J-K flip-flop with J = K = T and is used in counters.
- S-R
- Q(next) = S + R'Q, with SR = 0
- J-K
- Q(next) = JQ' + K'Q
- D
- Q(next) = D
- T
- Q(next) = T ⊕ Q
Topic 6
Applications of flip-flops
- Registers: a group of flip-flops stores a binary word (an 8-bit register uses 8 flip-flops).
- Shift registers: move data left or right for serial-parallel conversion.
- Counters: count clock pulses (T or J-K flip-flops).
- Frequency division: a T flip-flop divides the clock frequency by 2.
- Memory: static RAM cells are flip-flops.
- Debouncing switches and storing status flags in a CPU.
Key terms
- Flip-flop
- A clocked 1-bit memory element
- Latch
- A level-triggered 1-bit memory element
- Race-around
- Repeated toggling of a J-K flip-flop during one clock pulse
- Edge triggering
- Changing state only at the rising or falling edge of the clock
- Characteristic equation
- An expression for the next state of a flip-flop
Quick revision
- S-R: S = R = 1 is invalid.
- J-K: J = K = 1 toggles; race-around in level-triggered J-K.
- Master-Slave J-K removes race-around.
- D: Q(next) = D. T: Q(next) = T ⊕ Q.
- Flip-flops make registers, counters and memory.
Important exam questions
Practice questions written to the PTU exam pattern for this unit's syllabus: short answers (Section A style) and long answers (Sections B and C style).
Short-answer questions
- Q1.Differentiate between a latch and a flip-flop.
- Q2.Why is S = R = 1 not allowed in an S-R flip-flop?
- Q3.What is the race-around condition?
- Q4.Write the characteristic equation of a J-K flip-flop.
- Q5.How is a D flip-flop obtained from a J-K flip-flop?
- Q6.Give two applications of flip-flops.
Long-answer questions
- Q1.Explain the J-K flip-flop with its logic diagram and truth table. What is the race-around condition and how is it removed?
- Q2.Explain the working of a Master-Slave J-K flip-flop with a timing diagram.
- Q3.Explain D and T flip-flops and their applications.
- Q4.Differentiate between combinational and sequential circuits and explain the S-R flip-flop in detail.
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