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Unit 4 of 4 · B.Sc IT Sem 3

Unit 4: Stack and memory organization

Computer System Architecture notes · PTU syllabus (BSIT301/BSBC204)

3 min read9 topics10 exam questions
On this page
  1. Unit summary
  2. Stack organisation
  3. Memory hierarchy
  4. RAM and ROM chips
  5. Logical and physical addresses
  6. Associative memory
  7. Cache memory
  8. Cache mapping techniques
  9. Replacement algorithms
  10. Harvard and mobile device architectures
  11. Key terms
  12. Quick revision
  13. Important questions

Unit summary

Memory organisation balances speed, size and cost. This unit covers memory and register stacks, the memory hierarchy, RAM and ROM chips, logical and physical addresses, associative memory, cache memory — initialisation, writing, locality of reference and hit ratio — replacement algorithms (LRU, FIFO), direct, associative and set-associative mapping, Harvard architecture, and mobile device architectures.

After this unit you can

  • Explain register and memory stacks
  • Explain the memory hierarchy, RAM and ROM chips and associative memory
  • Explain cache memory, mapping and replacement
  • Explain Harvard and mobile device architectures

PTU syllabus topics

  • Memory and register stack
  • memory hierarchy
  • RAM/ROM chips
  • logical/physical addresses
  • associative memory
  • cache memory initialization/writing/locality of reference/hit ratio
  • replacement algorithms (LRU, FIFO)
  • direct/associative/set-associative mapping
  • Harvard architecture
  • mobile device architectures
ComparisonCache mapping techniques
How a block is placed
Trade-off

Direct

Exactly one possible line

Simple but more conflicts

Associative

Any line

Flexible but costly to search

Set-associative

Any line within one set

Balance of both

1

Topic 1

Stack organisation

  • Stack: last-in, first-out storage with a stack pointer (SP).
  • Register stack: a set of registers (e.g., 64 words) with SP, FULL and EMPTY flags; memory stack: part of main memory used as a stack (grows towards lower addresses).
Key formulasStack operations

  • PUSH

    SP ← SP − 1; M[SP] ← DR

  • POP

    DR ← M[SP]; SP ← SP + 1

  • Uses: subroutine calls and returns, evaluating postfix expressions (zero-address instructions), interrupts.
2

Topic 2

Memory hierarchy

HierarchyMemory hierarchy
  1. Registers

    Fastest, smallest

  2. Cache memory

    SRAM

  3. Main memory

    DRAM

  4. Secondary storage

    SSD, magnetic disk

  5. Tertiary storage

    Tape, optical, cloud archives

  • Moving down: larger capacity, lower cost per bit, slower access.
3

Topic 3

RAM and ROM chips

  • RAM chip: read-write; inputs — address lines, chip select (CS), read and write controls; data lines bidirectional. SRAM (flip-flops, fast, cache) vs DRAM (capacitors, needs refresh, main memory).
  • ROM chip: read-only; types — mask ROM, PROM, EPROM (UV erasable), EEPROM and flash (electrically erasable) — used for firmware (BIOS/UEFI).
  • Memory address map: assigns address ranges to each RAM and ROM chip.
4

Topic 4

Logical and physical addresses

  • Logical (virtual) address: generated by the CPU for a program. Physical address: actual location in main memory.
  • Memory management unit (MMU): maps logical to physical addresses (paging, segmentation), enabling virtual memory and protection.
5

Topic 5

Associative memory

  • Associative (content-addressable) memory: accessed by content rather than address — all words compared in parallel with an argument register under a key (mask) register.
  • Use: fast table look-ups such as translation lookaside buffers (TLB) and cache tags; expensive.
6

Topic 6

Cache memory

  • Locality of reference: programs reuse recent data (temporal) and nearby data (spatial).
Key formulasCache performance

  • Hit ratio

    Hits ÷ (hits + misses)

  • Average access time

    h × Tc + (1 − h) × (Tc + Tm); or h Tc + (1 − h) Tm when cache and memory are searched in parallel

Example

Hit ratio 0.9, cache 10 ns, memory 100 ns: average access ≈ 0.9 × 10 + 0.1 × 110 = 20 ns.

  • Writing: write-through (update memory every write — simple, consistent) vs write-back (update memory only when the block is replaced — faster, uses a dirty bit).
  • Initialisation: valid bits cleared at power-on so that all lines are treated as empty.
7

Topic 7

Cache mapping techniques

ComparisonMapping techniques
How a block is placed
Trade-off

Direct mapping

Block j goes to line j mod (number of lines)

Simple and cheap; conflict misses

Associative mapping

Block can go in any line; tags searched in parallel

Flexible; expensive comparison hardware

Set-associative mapping

Block maps to one set, any line within the set (k-way)

Balance of cost and hit ratio

8

Topic 8

Replacement algorithms

  • FIFO: replace the block that has been in the cache longest.
  • LRU (least recently used): replace the block not used for the longest time — usually better hit ratio.
  • Others: random, LFU (least frequently used), optimal (theoretical).
9

Topic 9

Harvard and mobile device architectures

  • Harvard architecture: separate memories and buses for instructions and data — simultaneous fetch; used in DSPs and microcontrollers; modern CPUs use a modified Harvard design with split L1 caches.
  • Mobile device architecture: system-on-chip (SoC) integrating ARM CPU cores (often big.LITTLE for power efficiency), GPU, neural processing unit, modem, image signal processor and memory controller; focus on low power and heat; examples — Qualcomm Snapdragon, Apple A-series, MediaTek Dimensity.

Key terms

Stack pointer
Register holding the address of the top of the stack
Locality of reference
Tendency to reuse recent and nearby data
Hit ratio
Fraction of accesses found in the cache
Set-associative mapping
Block placed in any line of one set
System-on-chip
Integrated chip with CPU, GPU and other units

Quick revision

  • Register and memory stacks; PUSH and POP.
  • Hierarchy: registers → cache → main → secondary → tertiary.
  • RAM (SRAM, DRAM), ROM types; address map; logical vs physical; MMU.
  • Associative memory; cache locality, hit ratio, write policies.
  • Direct, associative, set-associative mapping; FIFO, LRU; Harvard and mobile SoC.

Important exam questions

Practice questions written to the PTU exam pattern for this unit's syllabus: short answers (Section A style) and long answers (Sections B and C style).

Short-answer questions

  1. Q1.State the PUSH operation in RTL.
  2. Q2.Distinguish SRAM and DRAM.
  3. Q3.What is associative memory?
  4. Q4.Define hit ratio.
  5. Q5.Distinguish write-through and write-back.
  6. Q6.What is a system-on-chip?

Long-answer questions

  1. Q1.Explain register and memory stack organisation.
  2. Q2.Explain the memory hierarchy and RAM and ROM chips.
  3. Q3.Explain cache memory, its performance and mapping techniques.
  4. Q4.Explain replacement algorithms and Harvard and mobile device architectures.

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